The present invention relates to a manufacturing technique of a semiconductor device and to a semiconductor manufacturing apparatus and a technique of controlling transfer in a production line. It particularly relates to a technique effectively applied to a method for manufacture-starting lots in a process for manufacturing the semiconductor device.
In the recent manufacture of semiconductor devices, it is required to rapidly supply products to meet the needs of customers, and necessities of manufacturing the products at short TAT (Turn Around Time) are increasing to cope with such needs. Further, since product cycles become shortened, the shortening of TAT for developments of semiconductor products is strongly necessitated. It is particularly necessary to repeatedly perform adjustment of a manufacturing process, correction of mask patterns, and the like in developmental stages of new products. Therefore, it is of importance to shorten the TAT for manufacturing samples to shorten the development period for products.
For example, Japanese Patent Laid-open No. 2001-325013 discloses a technique of: in the case of allotting manufacturing steps for lots of high priority (hereinafter referred to as xe2x80x9cexpress lotsxe2x80x9d) in a manufacturing process of normal lots, suppressing a decrease in an utilization rate of the entire semiconductor manufacturing line; and dissolving the manufacture holdup of the express lots to manufacture the expresses lots for the minimum period. More particularly, one or more than one manufacturing apparatus capable of being allotted to an express-lot process compares process-finish time of the lots that is presently being processed and process-start estimated time of the express lots. Then, the express lot is allotted to such manufacturing apparatus that the process-finish time of the presently processing lots precedes the process-start estimated time of the express lots and that the process-finish time of the presently processing lots is latest. If all the process-finish time of the lots that are presently being processed in all of the corresponding manufacturing apparatuses are later than the process-start estimated time of the express lot, to such manufacturing apparatus that the process-finish time of the presently processing lots is latest, the presently processing lots is not transferred in advance and the manufacturing apparatus is kept empty until the processing of the express lot is started.
In production lines for semiconductor device, not to reduce the utilization rate of the manufacturing apparatus by the occurrence of the time required for the lots to wait for being transferred in the manufacturing apparatus, when a port of the manufacturing apparatus becomes empty, a dispatch system for lot gives order, which takes priority and FIFO (First-In First-Out) into consideration, to the lots standby in a stocker. Based on the order, an appropriate lot is transferred to the vacant port. Considering such a technique, the inventors of the present invention have found that the following problems are present.
Namely, when a vacant port occurs in the manufacturing apparatus, the dispatch system for lot immediately allots the appropriate lot to this vacant port to transfer this lot to the vacant port, whereby there is a possibility that time required for transferring first the express lot to the manufacturing apparatus will be not obtained. For this reason, there have been problems of the fact that the timing, in which manufacture progress of the express lots exceeds manufacture progress of the normal lots, is reduced and that shortening of the TAT for processing the express lots becomes impossible.
Also, in a production line for semiconductor device, the production line may be of a complicated system or it is required to use repeatedly the same manufacturing apparatus. Therefore, for example, by making a Gantt chart for all the manufacturing apparatuses in the production line in advance, a schedule of manufacture-start plans is made in detail and the lots are transferred to the manufacturing apparatus in accordance with this schedule and then the manufacturing of the lots starts. Considering such a technique, the inventors of the present invention have found that the following problems are present.
That is, if there occurs a time lag between the actual manufacture-start and process-finish times and the schedule made in advance, the lot-transfer waiting time occurs in the manufacturing apparatus and the utilization rate of the manufacturing apparatus is reduced. Thereby, there has been a problem of a reduction in the yield of the semiconductor device.
Also, if an accidental abnormality in a manufacturing apparatus (for example, occurrence of foreign matters or the like) occurs, it is required to remake the detailed schedule of the manufacture-start plans of all the manufacturing apparatuses in the production line. If such accidental abnormality occurs continuously, rescheduling is frequently performed and a complicated system or the like is required to have a high-speed scheduling tool with high reliability and to grasp the current status of the production line and the cost thereof increases. Therefore, there has been a problem of the fact that the manufacturing cost of the semiconductor device is increased.
An object of the present invention is to provide a technique capable of shortening the TAT for processing the express lots, without reducing the utilization rate of a device for manufacturing a semiconductor device.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Outlines of representative ones of the inventions disclosed in this application will be briefly described as follows.
More particularly, according to the present invention, a method for manufacturing a semiconductor device, which employs at least one first processing apparatus performing a first process to a lot, and at least one second processing apparatus having two or more than two ports and performing a second process to said lot, comprises the steps of:
(a) performing said first process to a first lot with a predetermined process priority by said first processing apparatus;
(b) performing said first process to a second lot lower in process priority than said first lot by said first processing apparatus;
(c) transferring said second lot to a first standby area when said step (b) is completed before said step (a) and only one of said ports is vacant in said second processing apparatus;
(d) transferring said first lot to the vacant port in said second processing apparatus after said step (a); and
(e) performing said second process to said first lot by said second processing apparatus.
Further, according to the present invention, a method for manufacturing a semiconductor device, which employs at least one first processing apparatus performing a first process to a lot, and at least one second processing apparatus having two or more than two ports and performing a second process to said lot, comprises the steps of:
(a) performing said first process to a first lot having a predetermined process priority by said first processing apparatus;
(b) performing said first process to a second lot lower in process priority than said first lot by said first processing apparatus;
(c) transferring said second lot to said ports which are vacant in said second processing apparatus after said step (b);
(d) transferring said second lot to a first standby area from said second processing apparatus and transferring said first lot to said ports vacant in said second processing apparatus when said step (a) is completed during or after said step (c) and when said second process for said second lot by said second processing apparatus stats not being performed; and
(e) performing said second process to said first lot by said second processing apparatus.
Further, according to the present invention, a semiconductor manufacturing apparatus comprises:
(a) at least one first processing apparatus performing a first process to a lot;
(b) a first standby area provided at a predetermined position;
(c) a second processing apparatus having two or more than two ports and performing a second process to said lot;
(d) a transfer apparatus transferring the lot to said first processing apparatus and said second processing apparatus; and
(e) a control means controlling said first processing apparatus, said second processing apparatus and said transfer apparatus,
wherein said control means controls said transfer apparatus such that:
(e1) in the presence of at least one vacant port in said second processing apparatus at the time of completing said first process for a first lot having a predetermined process priority by said first processing apparatus, transferring said first lot to said vacant port; and
(e2) in the absence of two or more of said vacant ports in said second processing apparatus at the time of completing said first process to a second lot lower in process priority than said first lot by said first processing apparatus, transferring said second lot to said first standby area.
Further, according to the present invention, a semiconductor manufacturing apparatus comprises:
(a) at least one first processing apparatus performing a first process to a lot;
(b) a first standby area provided at a predetermined position;
(c) a second processing apparatus having two or more than two ports and performing a second process to said lot;
(d) a transfer apparatus transferring said lot to said first processing apparatus and said second processing apparatus; and
(e) a control means controlling said first processing apparatus, said second processing apparatus and said transfer apparatus,
wherein said control means controls said transfer apparatus such that:
(e1) at the time of completing said first process of a second lot lower in process priority than a first lot having a predetermined process priority by the first processing apparatus, said second lot is transferred to the ports vacant in said second processing apparatus; and
(e2) when said first process of said first lot by the first processing apparatus is completed during or after the transfer of said second lot to the ports vacant in said second processing apparatus and when said second process for said second lot by said second processing apparatus starts not being performed, said second lot is transferred to a first standby area from said second processing apparatus and said first lot is transferred to said vacant port in said second processing apparatus.